The present invention relates to dynamic random access memory, and more specifically, to memory systems with multiple dynamic random access memory modules.
Dynamic random access memory (DRAM) is a general-purpose high-performance memory device suitable for use in a broad range of applications.
FIG. 1 illustrates a prior art memory system. A memory channel 160 is coupled to a master device 110. Master 110 sends requests (commands) 160 to memories 120 and sends and receives data 170 from memories 120. The memories 120 receive the clock-from-master (CFM) 140 and clock-to-master (CTM) 150 signals generated by clock 130. CFM 140 is used to send commands 160 and write data 170 to the memories 120. CTM is used to receive data 170 from the memories 120.
The CFM 140 and CTM 150 signal lines may either be coupled together inside the master 110 or just outside the master 110, having a single clock signal connected into the master 110. At the master device 110, CTM 150 and CFM 140 have the same phase and are not delayed with respect to each other. However, for memories located some distance away from the master, the phase difference between CFM 140 and CTM 150 may be significant. The channel 160 may be long enough to allow the delay between CTM 150 and CFM 140 to be several clock periods apart. A segment of the channel 160 that is characterized by a half clock cycle of data flight time delay represents a timing domain. In addition, a timing domain may be defined as a segment of the channel 160 in which the phase difference between CTM 150 and CFM 140 is equal to a full clock cycle. The second definition applies to reading data from memories 120. When a read command is performed, there is a round-trip delay between sending the command and receiving read data at master 110. As a result, the half clock cycle of data flight time is doubled and becomes a full clock cycle of delay.
Current memory systems, such as the memory system 100, typically do not support the length of channel 160 that exceeds four timing domains. The limited range of timing domains (also known as tTR) limits the number of memory devices 120 that can be supported by the channel 160. In one prior art system, memory system 100 may provide for up to 32 memory devices 120 on the channel 160. A number of slots may be provided on channel 160 to receive memory devices 120, such as Rambus Inline Memory Modules (RIMMs(trademark)) which can support up to eight memory devices on each side of the module. If the physical length of the channel 160 is limited to four timing domains, it may be insufficient for 32 memory devices on more than two memory modules. In addition, some computer systems, such as systems that support large databases, have a need for large memory subsystems made possible by 64 bit computer architectures. In these computer systems being able to support more than 32 memory devices is advantageous.
A method for extending tTR range of memory devices is provided in which a first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. Data from the first and second groups is received.